diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-26 06:15:35 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-02 17:43:51 +0000 |
| commit | 45a670d223ce7e77a4ba1e5d6419753d2e6a558d (patch) | |
| tree | 9c588cca7797e926bfdf05167261031f0391fa9b /src/mainboard/inventec | |
| parent | a0aff6e15988f918b926c4cd222537d2f5a3f878 (diff) | |
soc/intel/xeon_sp: Move VPD based settings to mainboard codes
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/inventec')
| -rw-r--r-- | src/mainboard/inventec/transformers/romstage.c | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 9299c7dc04..1abcf708a9 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -98,22 +98,28 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { init_frb2_wdt(); } - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } } + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */ |