diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-05-26 08:11:51 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-04 03:45:43 +0000 |
| commit | e9ee4390a5f638caf9e86f5782a2d237c04f0baf (patch) | |
| tree | 8a62aa47481edf33b14659c821694319c893a35b /src/mainboard/intel | |
| parent | 542a2d908defd5a0aa01cda1e850cf37dcb7a1ca (diff) | |
soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI
This CL also enables HECI 1 in devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index dde0e9bb98..fa82a68bb5 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,11 +12,21 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci1 communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "Heci2Enable" = "1" + # Display related UPDs + # Enable HPD for DDI ports C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports C + register "DdiPortCDdc" = "1" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" @@ -104,6 +114,10 @@ chip soc/intel/elkhartlake # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |