diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-04-30 14:57:51 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 19:27:34 +0200 |
| commit | e6063fee5c954d5acd80fd51e11aeac31e83d13d (patch) | |
| tree | 331b26df9de6e8b4e08473432de1d293602487df /src/mainboard/intel | |
| parent | a1155b47ca42ad1813c36e1d6de6e8116ae13845 (diff) | |
Fix Sandybridge/Ivybridge mainboards according to code review
This fixes a few cosmetics with the following three boards:
- Intel Emerald Lake 2
- Samsung ChromeBook
- Samsung ChromeBox
The following issues were fixed:
- rely on include path in ASL code instead of specifying relative
paths
- use updated ALIGN_CURRENT in acpi_tables.c
- use preprocessor defines instead of hard coded values where possible
Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/acpi/superio.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 18 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index f803aaf8b9..a50c4b3aa3 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -32,4 +32,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "../../../../superio/smsc/sio1007/acpi/superio.asl" +#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index c84ac46a3d..01d4b5492e 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -180,7 +180,7 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 23d1d6b37c..0cf113b9f3 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -188,17 +188,17 @@ void main(unsigned long bist) #endif struct pei_data pei_data = { pei_version: PEI_VERSION, - mchbar: 0xfed10000, - dmibar: 0xfed18000, - epbar: 0xfed19000, - pciexbar: 0xf0000000, - smbusbar: 0x400, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, - hpet_address: 0xfed00000, - rcba: 0xfed1c000, - pmbase: 0x500, - gpiobase: 0x480, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBABASE, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, thermalbase: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, |