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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2023-06-08 19:08:57 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-06-12 15:27:31 +0000
commite06d786d0b64a96ab7c20d0b3871df38d1d451e1 (patch)
tree373c5fb5c1f047266c0f3c37b869719380dc2825 /src/mainboard/intel
parent11ef816cf0465fe09cf8aa0f469b8ce2ce2f41bd (diff)
mb/intel/mtlrvp: Add CPU power limit values
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard. BRANCH=None BUG=None TEST=Built the changes Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/mtlrvp/Kconfig1
-rw-r--r--src/mainboard/intel/mtlrvp/mainboard.c7
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h3
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc1
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c28
5 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index ea6c6cb08a..4f4526e0c6 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -17,6 +17,7 @@ config BOARD_INTEL_MTLRVP_COMMON
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE_U_P
diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c
index 9621294e2c..2e515f7137 100644
--- a/src/mainboard/intel/mtlrvp/mainboard.c
+++ b/src/mainboard/intel/mtlrvp/mainboard.c
@@ -35,6 +35,13 @@ static void mainboard_init(void *chip_info)
if (CONFIG(EC_GOOGLE_CHROMEEC))
mainboard_ec_init();
+
+ variant_devtree_update();
+}
+
+void __weak variant_devtree_update(void)
+{
+ /* Override dev tree settings per board */
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
index f755ff0238..726a61721a 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
@@ -20,4 +20,7 @@ void configure_gpio_pads(void);
/* Function to initialize memory params based on variant */
const struct mb_cfg *variant_memory_params(void);
+/* Modify devictree settings during ramstage */
+void variant_devtree_update(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
index cc5cdc1ace..dafb64b491 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
@@ -2,3 +2,4 @@
bootblock-y += gpio.c
ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
new file mode 100644
index 0000000000..aee3d888a1
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+const struct cpu_tdp_power_limits limits[] = {
+ {
+ .mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+ .cpu_tdp = 15,
+ .pl1_min_power = 10000,
+ .pl1_max_power = 15000,
+ .pl2_min_power = 57000,
+ .pl2_max_power = 57000,
+ .pl4_power = 114000
+ },
+};
+
+void variant_devtree_update(void)
+{
+ size_t total_entries = ARRAY_SIZE(limits);
+ variant_update_cpu_power_limits(limits, total_entries);
+}