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authorPratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>2023-06-21 18:34:40 -0700
committerSubrata Banik <subratabanik@google.com>2023-06-23 13:45:29 +0000
commitbb4bc777b7b6566cd030f2c4eef4b5e2c8425349 (patch)
treeebcd5e02a2c266302b392753e4c0016a44fa8260 /src/mainboard/intel
parentb1d3f3d7bf32af1fde8498dfec572310885c38e0 (diff)
soc/intel/meteorlake: Rename shared SRAM aliases
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 05a61be1fe..b7ce90daeb 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -583,7 +583,7 @@ chip soc/intel/meteorlake
end # I2C3
device ref i2c4 on end
device ref i2c5 on end
- device ref shared_sram on end
+ device ref pmc_shared_sram on end
device ref uart0 on end
device ref gspi1 on end
device ref smbus on end