Final set of smp_write_bus -> mptable_write_buses changes.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 12 insertions, 52 deletions

diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 2c814d9e49..e9415bff48 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -61,9 +61,9 @@
 static void *smp_write_config_table(void *v)
 {
         struct mp_config_table *mc;
-	unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
+	unsigned char bus_chipset, bus_pci;
 	unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
-	int i;
+	int bus_isa, i;
 	uint32_t pin, route;
 	device_t dev;
 	struct resource *res;
@@ -89,12 +89,9 @@ static void *smp_write_config_table(void *v)
 	dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
 	if (dev) {
 	  bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	  bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-	  bus_isa++;
 	} else {
 	  printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
 	  bus_pci = 6;
-	  bus_isa = 7;
 	}
 
 	dev = dev_find_slot(0, PCI_DEVFN(2,0));
@@ -121,11 +118,7 @@ static void *smp_write_config_table(void *v)
 	  bus_pcie_b = 3;
 	}
 
-	/*Bus: Bus ID Type*/
-	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
-	  smp_write_bus(mc, bus_num, "PCI   ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA   ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/*I/O APICs: APIC ID Version State Address*/
 	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 38528299dc..68e6a9af65 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -8,8 +8,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	unsigned char bus_num;
-	unsigned char bus_isa;
+	int bus_isa;
 	unsigned char bus_pxhd_1;
 	unsigned char bus_pxhd_2;
 	unsigned char bus_pxhd_3 = 0;
@@ -31,14 +30,11 @@ static void *smp_write_config_table(void *v)
 		dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
 		if (dev) {
 			bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-			bus_isa++;
 		}
 		else {
 			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
 
 			bus_ich5r_1 = 4;
-			bus_isa = 5;
 		}
 		/* pxhd-1 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
@@ -88,11 +84,7 @@ static void *smp_write_config_table(void *v)
 		}
 	}
 
-	/* define bus and isa numbers */
-	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
-		smp_write_bus(mc, bus_num, "PCI	  ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA	  ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* IOAPIC handling */
 
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 9dccf13e0f..a13242b69b 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -29,7 +29,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	u8 bus_isa = 7;
+	int bus_isa;
 	u8 bus_pci = 6;
 	u8 bus_pcie_a = 1;
 
@@ -39,11 +39,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	/* Define bus numbers */
-	smp_write_bus(mc, 0, "PCI   ");
-	smp_write_bus(mc, bus_pci, "PCI   ");
-	smp_write_bus(mc, bus_pcie_a, "PCI   ");
-	smp_write_bus(mc, bus_isa, "ISA   ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* IOAPIC handling */
 	smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index e691f836ee..6fff9c4275 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -27,8 +27,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	u8 bus_num;
-	u8 bus_isa;
+	int bus_isa;
 	u8 bus_pea0 = 0;
 	u8 bus_pea1 = 0;
 	u8 bus_aioc;
@@ -44,13 +43,10 @@ static void *smp_write_config_table(void *v)
 	dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
 	if (dev) {
 		bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		bus_isa++;
 	}
 	else {
 		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
 		bus_aioc = 0;
-		bus_isa = 9;
 	}
 	/* PCIe A0 */
 	dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
@@ -71,11 +67,7 @@ static void *smp_write_config_table(void *v)
 		bus_pea1 = 0;
 	}
 
-	/* define bus and isa numbers */
-	for(bus_num = 0; bus_num < bus_isa; bus_num++) {
-		smp_write_bus(mc, bus_num, "PCI	  ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA	  ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* IOAPIC handling */
 	smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h
index 2378ceaea0..286120acf2 100644
--- a/src/mainboard/intel/xe7501devkit/bus.h
+++ b/src/mainboard/intel/xe7501devkit/bus.h
@@ -12,6 +12,5 @@
 #define PCI_BUS_P64H2_1_B	5		// P64H2#1 bus B
 #define PCI_BUS_P64H2_1_A	6		// P64H2#1 bus A
 #define PCI_BUS_ICH3		7		// ICH3-S
-#define SUPERIO_BUS			8		// (arbitrary but unique bus #)
 
 #endif	// XE7501DEVKIT_BUS_H_INCLUDED
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 1a9268061d..9213a2389e 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -15,19 +15,7 @@
 #define INT_D	3
 #define PCI_IRQ(dev, intLine)	(((dev)<<2) | intLine)
 
-static void xe7501devkit_register_buses(struct mp_config_table *mc)
-{
-	// Bus ID, Bus Type
-	smp_write_bus(mc, PCI_BUS_CHIPSET,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_E7501_HI_B,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_P64H2_2_B,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_P64H2_2_A,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_E7501_HI_D,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_P64H2_1_B,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_P64H2_1_A,	BUSTYPE_PCI);
-	smp_write_bus(mc, PCI_BUS_ICH3,		BUSTYPE_PCI);
-	smp_write_bus(mc, SUPERIO_BUS,		BUSTYPE_ISA);
-}
+static int bus_isa;
 
 static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 {
@@ -126,7 +114,7 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 
 	// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
 
-	mptable_add_isa_interrupts(mc, SUPERIO_BUS, IOAPIC_ICH3, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
 }
 
 static void *smp_write_config_table(void* v)
@@ -139,7 +127,7 @@ static void *smp_write_config_table(void* v)
 
 	smp_write_processors(mc);
 
-	xe7501devkit_register_buses(mc);
+	mptable_write_buses(mc, NULL, &bus_isa);
 	xe7501devkit_register_ioapics(mc);
 	xe7501devkit_register_interrupts(mc);