diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:52:11 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 10:49:11 +0000 |
| commit | 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 (patch) | |
| tree | 4f21a3de147f422336545ed3164581b6b80c45d7 /src/mainboard/intel | |
| parent | 0a97e466163dda4e55c1eda145646054dcd8dd06 (diff) | |
mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
20 files changed, 20 insertions, 62 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4c5b0c61f6..70a8706803 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,9 +6,7 @@ fw_config end chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index 5421dc3262..ef361b0c85 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index e890082111..ea8b4e6576 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/xeon_sp/cpx - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host bridge device pci 04.0 on end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index e0ea3f20fa..051eba023c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index a1455848e9..2269d740ed 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index af5fc2de94..b6bf5a8852 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index f20622c9df..ce46c637ea 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 55b340caf3..b9fe4236e2 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index dc8874afe6..9c080230e0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 0464b7489f..82735c6556 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -5,11 +5,7 @@ chip northbridge/intel/pineview # Northbridge register "use_crt" = "true" register "use_lvds" = "false" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d3d114232d..2c952bf9c1 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 6ab391e36b..45fb7361ba 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index bae6198118..bf1b235914 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -109,9 +109,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 3fffc4a80e..5c5382fbaa 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,9 +150,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index deb9f38c7a..bc068c6d69 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -157,9 +157,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 76362e663e..add83fe437 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 76362e663e..add83fe437 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7cf13ec964..fcd99ac610 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -192,9 +192,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 8d80095019..932a5c755d 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 848b0c31c5..d44a1b64ab 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -80,9 +80,7 @@ chip soc/intel/braswell # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router |