diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-04 18:19:14 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 19:55:49 +0000 |
| commit | 584af87483899f49f30039aa7d5861a50ce73612 (patch) | |
| tree | 574941b54efed52e89359e6d5e63181c8e111869 /src/mainboard/intel | |
| parent | 0b21ad9e8012dba2f4365bfbc3b51e6637eec588 (diff) | |
intel/cannonlake_rvp: Enable Audio DSP
Enable Audio DSP by default on cannonlake rvp platform.
TEST=Boot up into OS and check Audio driver debug print.
Change-Id: I6892c6d349019550c967ef30b84d385f396fc388
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 627e7d25a6..b80cd82d50 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/cannonlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index d417e9057e..9a0ab64672 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/cannonlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" |