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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-03-24 16:26:02 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-03-26 06:18:31 +0000
commit5504cdb51150b8bc86f4ac0cece6fd746fc7510b (patch)
tree677bc29b2f7d7e16d053164889325921beebb9b3 /src/mainboard/intel
parent4dd857723b298512d22c6626e6bdc6d8c4b05234 (diff)
mb/intel/adlrvp: Remove static VBT stitching
Currently, we used to stitch extra VBT files to ADLRVP build using Makefile. With enablement of emerge build, we should be able to integrate more than 1 VBT binaries using ebuild. This removing these lines to avoid compilation issues in emerge builds BUG=None BRANCH=None TEST=Check if compilation passes on emerge build. Stitched additional VBT files using emerge and checked that coreboot picks up correct VBT. Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/Makefile.inc5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index 12f546b2e3..75c8cf8e20 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -19,11 +19,6 @@ ramstage-y += mainboard.c
ramstage-y += board_id.c
ramstage-y += gpio.c
-ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
-$(call add_vbt_to_cbfs, vbt_lp5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_lp5.bin)
-$(call add_vbt_to_cbfs, vbt_ddr5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_ddr5.bin)
-endif
-
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
subdirs-y += variants/$(VARIANT_DIR)