diff options
| author | Simon Glass <sjg@chromium.org> | 2018-05-23 15:34:04 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-25 20:50:14 +0000 |
| commit | 4f16049f17a4dcbf329d6b30f0d00f0a7f5490bf (patch) | |
| tree | fc85f157c406d075af7b9423fe9193aae2b2d72c /src/mainboard/intel | |
| parent | 57ccb9c5e859f515aa4f07e6bf81a9f2ae58a988 (diff) | |
mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions