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authorRonald G. Minnich <rminnich@gmail.com>2016-11-12 07:31:16 -0800
committerRonald G. Minnich <rminnich@gmail.com>2016-11-14 01:09:12 +0100
commit3d302b03f46fa6ed5927cdc2ef9f53b9ce0262ae (patch)
tree4d509bb2bbf0cdb62ba7cd3b035b22416511afdb /src/mainboard/intel
parent42c1e43cb16b26925611335bdc97808dae745af5 (diff)
riscv: add a variable to control trap management
This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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