diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2013-01-11 09:54:55 -0800 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-17 22:52:32 +0100 |
commit | 218a6864ff9528ecdb381d91991c9045bbb6843f (patch) | |
tree | 1f7f1d81486d36e804c5f416e2b42d71c59eb0f3 /src/mainboard/intel/wtm1/dsdt.asl | |
parent | c9fc0297ad6a63d9edf981a46f29f9372d11634c (diff) |
Add Intel Whitetip Mountain 1 mainboard
Lots of things are still placeholder and need work.
Due to the useful GPIOs being run to either the EC or the SIO1007
I have hard coded developer mode on and recovery mode off.
Change-Id: I4c308bd90db03ac5bffdfde566e5adbbaabac632
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2724
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/wtm1/dsdt.asl')
-rw-r--r-- | src/mainboard/intel/wtm1/dsdt.asl | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/intel/wtm1/dsdt.asl b/src/mainboard/intel/wtm1/dsdt.asl new file mode 100644 index 0000000000..965f5014cd --- /dev/null +++ b/src/mainboard/intel/wtm1/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include "../../../cpu/intel/haswell/acpi/cpu.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} |