diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 19:12:55 +0000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:33:14 +0000 |
| commit | ad50b40eed3f7f235e848a2382ffbee6a51d1755 (patch) | |
| tree | b8791e9c965c0b89d92e6d70d1635b99e184ba7a /src/mainboard/intel/tglrvp/variants | |
| parent | a2f51f222549035b27578cb084e13219443ca4b6 (diff) | |
soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d01fdd6352..2c9a548ae0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c0adcc3f50..d19747a5c0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" |