soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver

This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.

TEST=Verified that UPDs are configured correctly with and without this
change.

Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

1 files changed, 39 insertions, 37 deletions

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
index ca60357e84..8e7bb14ba0 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
@@ -9,59 +9,61 @@ size_t __weak variant_memory_sku(void)
 	return 0;
 }
 
-static const struct lpddr4x_cfg mem_config = {
+static const struct mb_cfg mem_config = {
+	.type = MEM_TYPE_LP4X,
+
 	/* DQ byte map */
-	.dq_map = {
-		[0] = {
-			{ 8,  9, 12,  11, 13, 15,  10, 14, }, /* DDR0_DQ0[7:0] */
-			{ 4,  6,  0,   2,  5,  7,   1,  3, }, /* DDR0_DQ1[7:0] */
+	.lp4x_dq_map = {
+		.ddr0 = {
+			.dq0 = { 8,  9, 12,  11, 13, 15,  10, 14, }, /* DDR0_DQ0[7:0] */
+			.dq1 = { 4,  6,  0,   2,  5,  7,   1,  3, }, /* DDR0_DQ1[7:0] */
 		},
-		[1] = {
-			{  2,  3,  0,   6,  1,  7,   5,  4, },  /* DDR1_DQ0[7:0] */
-			{ 15, 14, 13,   8, 12, 11,   9, 10, },  /* DDR1_DQ1[7:0] */
+		.ddr1 = {
+			.dq0 = {  2,  3,  0,   6,  1,  7,   5,  4, },  /* DDR1_DQ0[7:0] */
+			.dq1 = { 15, 14, 13,   8, 12, 11,   9, 10, },  /* DDR1_DQ1[7:0] */
 		},
-		[2] = {
-			{  1,  0,  3,   2,  5,  4,   7,  6, }, /* DDR2_DQ0[7:0] */
-			{ 14, 15, 12,  13,  8, 10,   9, 11, }, /* DDR2_DQ1[7:0] */
+		.ddr2 = {
+			.dq0 = {  1,  0,  3,   2,  5,  4,   7,  6, }, /* DDR2_DQ0[7:0] */
+			.dq1 = { 14, 15, 12,  13,  8, 10,   9, 11, }, /* DDR2_DQ1[7:0] */
 		},
-		[3] = {
-			{  8, 10, 11,   9, 15, 12,  14, 13, }, /* DDR3_DQ0[7:0] */
-			{  4,  7,  6,   5,  2,  0,  1,  3, },  /* DDR3_DQ1[7:0] */
+		.ddr3 = {
+			.dq0 = {  8, 10, 11,   9, 15, 12,  14, 13, }, /* DDR3_DQ0[7:0] */
+			.dq1 = {  4,  7,  6,   5,  2,  0,  1,  3, },  /* DDR3_DQ1[7:0] */
 		},
-		[4] = {
-			{  8,  9, 10,  11, 13, 12,  15, 14, }, /* DDR4_DQ0[7:0] */
-			{  7,  6,  4,   5,  0,  2,   1,  3, }, /* DDR4_DQ1[7:0] */
+		.ddr4 = {
+			.dq0 = {  8,  9, 10,  11, 13, 12,  15, 14, }, /* DDR4_DQ0[7:0] */
+			.dq1 = {  7,  6,  4,   5,  0,  2,   1,  3, }, /* DDR4_DQ1[7:0] */
 		},
-		[5] = {
-			{  1,  3,  0,   2,  6,  4,   5,  7, }, /* DDR5_DQ0[7:0] */
-			{ 14, 15, 10,  12,  8, 13,  11,  9, }, /* DDR5_DQ1[7:0] */
+		.ddr5 = {
+			.dq0 = {  1,  3,  0,   2,  6,  4,   5,  7, }, /* DDR5_DQ0[7:0] */
+			.dq1 = { 14, 15, 10,  12,  8, 13,  11,  9, }, /* DDR5_DQ1[7:0] */
 		},
-		[6] = {
-			{  1,  0,  2,   4,  5,  3,   7,  6, }, /* DDR6_DQ0[7:0] */
-			{ 12, 14, 15,  13,  9,  10,  8, 11, }, /* DDR6_DQ1[7:0] */
+		.ddr6 = {
+			.dq0 = {  1,  0,  2,   4,  5,  3,   7,  6, }, /* DDR6_DQ0[7:0] */
+			.dq1 = { 12, 14, 15,  13,  9,  10,  8, 11, }, /* DDR6_DQ1[7:0] */
 		},
-		[7] = {
-			{ 11,  9,  8,  13, 12,  14, 15, 10, }, /* DDR7_DQ0[7:0] */
-			{  4,  7,  5,   1,  2,   6,  3,  0, }, /* DDR7_DQ1[7:0] */
+		.ddr7 = {
+			.dq0 = { 11,  9,  8,  13, 12,  14, 15, 10, }, /* DDR7_DQ0[7:0] */
+			.dq1 = {  4,  7,  5,   1,  2,   6,  3,  0, }, /* DDR7_DQ1[7:0] */
 		},
 	},
 
 	/* DQS CPU<>DRAM map */
-	.dqs_map = {
-		[0] = { 1, 0 }, /* DDR0_DQS[1:0] */
-		[1] = { 0, 1 }, /* DDR1_DQS[1:0] */
-		[2] = { 0, 1 }, /* DDR2_DQS[1:0] */
-		[3] = { 1, 0 }, /* DDR3_DQS[1:0] */
-		[4] = { 1, 0 }, /* DDR4_DQS[1:0] */
-		[5] = { 0, 1 }, /* DDR5_DQS[1:0] */
-		[6] = { 0, 1 }, /* DDR6_DQS[1:0] */
-		[7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+	.lp4x_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */
 	},
 
-	.ect = 1, /* Early Command Training */
+	.ect = true, /* Early Command Training */
 };
 
-const struct lpddr4x_cfg *__weak variant_memory_params(void)
+const struct mb_cfg *__weak variant_memory_params(void)
 {
 	return &mem_config;
 }