diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-21 21:54:14 -0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-24 09:53:14 +0000 |
| commit | d250063c09d432cff563331a3dfb158d7c6a7a46 (patch) | |
| tree | 382a06863e41a9b1d29980eb7ff51fb64a2aa40a /src/mainboard/intel/tglrvp/variants/tglrvp_up3 | |
| parent | 815d96a975d67db73b8299b3c521b74cf9725b99 (diff) | |
mb/intel/tglrvp: Enable SATA
Enable both SATA ports for TGLRVP.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39dce..01e0f3f8f8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,10 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -122,7 +126,7 @@ chip soc/intel/tigerlake device pci 16.3 off end # CSME 0xA0E3 device pci 16.4 off end # HECI3 0xA0E4 device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 off end # SATA 0xA0D3 + device pci 17.0 on end # SATA 0xA0D3 device pci 19.0 off end # I2C4 0xA0C5 device pci 19.1 on end # I2C5 0xA0C6 device pci 19.2 on end # UART2 0xA0C7 |