diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-27 22:58:52 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-29 20:03:50 +0000 |
| commit | bc8f5405b542eef35a71e5189d71654cbe134558 (patch) | |
| tree | 289b1339565fb614281b31e07f09bb933c1465b8 /src/mainboard/intel/tglrvp/variants/tglrvp_up3 | |
| parent | 0adf35537bd6093b79b1701becee823d3436d975 (diff) | |
tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ecad52e60a..1bce4b20a8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -14,20 +14,6 @@ chip soc/intel/tigerlake # CNVi BT enable/disable register "CnviBtCore" = "true" - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - # CPU replacement check register "CpuReplacementCheck" = "1" @@ -206,7 +192,25 @@ chip soc/intel/tigerlake end device ref gspi2 off end device ref gspi3 off end - device ref south_xhci on end + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // Type-C Port1 + [1] = USB2_PORT_EMPTY, // M.2 WWAN + [2] = USB2_PORT_MID(OC3), // M.2 Bluetooth + [3] = USB2_PORT_MID(OC0), // USB3/2 Type A port1 + [4] = USB2_PORT_MID(OC0), // Type-C Port2 + [5] = USB2_PORT_MID(OC3), // Type-C Port3 + [6] = USB2_PORT_MID(OC3), // Type-C Port4 + [7] = USB2_PORT_MID(OC0), // USB3/2 Type A port2 + [8] = USB2_PORT_MID(OC3), // USB2 Type A port3 + [9] = USB2_PORT_MID(OC3), // USB2 Type A port4 + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port1 + [1] = USB3_PORT_DEFAULT(OC0), // USB3/2 Type A port2 + }" + end device ref south_xdci on end device ref shared_ram on end device ref cnvi_wifi on |