diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-28 06:28:43 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-05 20:55:19 +0000 |
| commit | 9b31a90e7fda68ad1b03b65fc295fad9a6a3986f (patch) | |
| tree | f72076897adbcea0a11db50d240b2bdc6d69bba8 /src/mainboard/intel/tglrvp/variants/tglrvp_up3 | |
| parent | d9cb2c12d7f6fde26b736fe5fe1ca3f5142b1f18 (diff) | |
tgl mainboards: Move PCIe root port settings into their device scope
Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 42 |
1 files changed, 20 insertions, 22 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 9c5fa6da32..b82f583c76 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -17,28 +17,9 @@ chip soc/intel/tigerlake # CPU replacement check register "CpuReplacementCheck" = "1" - register "PcieRpSlotImplemented[2]" = "1" - register "PcieRpSlotImplemented[3]" = "1" - register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpSlotImplemented[10]" = "1" - - # Enable RP LTR - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[3]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Hybrid storage mode register "HybridStorageMode" = "1" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - - register "PcieClkSrcUsage[1]" = "0x2" - register "PcieClkSrcUsage[2]" = "0x3" - register "PcieClkSrcUsage[3]" = "0x8" - # enabling EDP in PortA register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -260,8 +241,17 @@ chip soc/intel/tigerlake device ref uart2 on end device ref pcie_rp1 off end device ref pcie_rp2 off end - device ref pcie_rp3 on end + device ref pcie_rp3 on + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieClkSrcUsage[1]" = "0x2" + register "PcieClkSrcClkReq[1]" = "1" + end device ref pcie_rp4 on + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieClkSrcUsage[2]" = "0x3" + register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" register "srcclk_pin" = "2" @@ -272,9 +262,17 @@ chip soc/intel/tigerlake device ref pcie_rp6 off end device ref pcie_rp7 off end device ref pcie_rp8 off end - device ref pcie_rp9 on end + device ref pcie_rp9 on + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "0x8" + register "PcieClkSrcClkReq[3]" = "3" + end device ref pcie_rp10 off end - device ref pcie_rp11 on end + device ref pcie_rp11 on + register "PcieRpSlotImplemented[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + end device ref pcie_rp12 off end device ref uart0 off end device ref uart1 off end |