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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-02-19 00:48:55 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-26 17:08:36 +0000
commitfdba0cd6af05f9317dbd19956d644ce01e37a547 (patch)
treeddaedb4aef31acee0af965c0382128dea5e517fa /src/mainboard/intel/tglrvp/variants/baseboard/include
parent1f9112f798c127fc9fa50f6f927dcea84baa1845 (diff)
mb/intel/tglrvp: add Tiger Lake memory initialization support
Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/baseboard/include')
-rw-r--r--src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
index 9220b1140c..25c9755d9d 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@
#define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h>
+#include <soc/meminit_tgl.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -27,4 +28,7 @@ const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
+size_t variant_memory_sku(void);
+const struct mb_lpddr4x_cfg *variant_memory_params(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */