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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-12 09:58:05 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-17 22:28:13 +0000 |
| commit | 49889007891de8830428c3092cc6b0977ca165eb (patch) | |
| tree | 2702b0c9cdebc01194cf4b7fcfc70e8b4ed7ae19 /src/mainboard/intel/tglrvp/smihandler.c | |
| parent | 286c2f6d4a72473b919ea580786d5497f7ef2dec (diff) | |
soc/intel/alderlake: Fix PCI IRQ tables
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.
BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/smihandler.c')
0 files changed, 0 insertions, 0 deletions