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| author | Robert Zieba <robertzieba@google.com> | 2022-09-19 10:26:51 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-09 19:41:33 +0000 |
| commit | 6998ee069a33ab56307c43a4108276a020fc713f (patch) | |
| tree | 8e88a8bb8fda6d1e51cebf20b29a25096a7935eb /src/mainboard/intel/tglrvp/ec.c | |
| parent | 3db7b46804fd69cd7443e4c007248c4acff9f97a (diff) | |
soc/amd/cezanne: Set up SoC-specific XHCI definitions
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.
BRANCH=guybrush
BUG=b:186792595
TEST=builds
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/ec.c')
0 files changed, 0 insertions, 0 deletions