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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-08-27 16:41:42 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-23 18:52:28 +0000
commitca128a0eb42dfc41c80aef9659dae06274dd65b3 (patch)
tree48f88f06f62ce40b9e9e5b82031ae2900c2b6c95 /src/mainboard/intel/tglrvp/board_id.c
parent5b7daa224cb035f87c3b71105bb453849c7d54d4 (diff)
mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP
BUG=none TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated. cat /sys/devices/system/cpu/intel_pstate/ Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609 Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/board_id.c')
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