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| author | Subrata Banik <subrata.banik@intel.com> | 2021-05-04 23:43:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-05-12 06:16:21 +0000 |
| commit | 86b1b6811c1c2cf47bdd7d662eb1865d83f60359 (patch) | |
| tree | ed906a6e7b3c65f20ada4f1de2e19dd5e5043088 /src/mainboard/intel/tglrvp/board_id.c | |
| parent | 8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c (diff) | |
include/console: Fix FSP Notify phase postcodes discrepancy
List of changes:
1. Make the FSP notify phases name prior in comments section.
2. Fix discrepancies in FSP notify before and after postcode comments.
3. Add FSP notify postcode macros for after pci enumeration(0xa2)
and ready to boot(0xa3) call.
Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/board_id.c')
0 files changed, 0 insertions, 0 deletions