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authorRizwan Qureshi <rizwan.qureshi@intel.com>2021-04-06 20:05:04 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-04-23 14:49:09 +0000
commit9452aab4d3656eca479b1f1c0ff4350ea2d04978 (patch)
treeb3c8ca4dd0aa636b3773060ca31b02bc72f5e431 /src/mainboard/intel/shadowmountain/variants/baseboard
parenta66b816675fc299e03092ef8d7b2c59f04641fb7 (diff)
mb/intel/shadowmountain: Enable RTD3 for SD card
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and specify the srcclk pin and reset GPIO. TEST=Tested on shadowmountain platform to ensure the system can enter the S0ix state and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/variants/baseboard')
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index f96844cd46..7b0edadccb 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -294,7 +294,13 @@ chip soc/intel/alderlake
device pci 1c.4 on end # RP5
device pci 1c.5 off end # RP6
device pci 1c.6 off end # RP7
- device pci 1c.7 on end # RP8
+ device pci 1c.7 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
+ register "srcclk_pin" = "3"
+ device generic 0 on end
+ end
+ end # RP8
device pci 1d.0 on end # RP9
device pci 1d.1 off end # RP10
device pci 1d.2 off end # RP11