diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-06-09 21:57:49 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-06-16 03:50:20 +0000 |
| commit | 8a18bd8500fee7c43e257d3dfd1cc3f7db82c88c (patch) | |
| tree | a171471b3dd21893f6b3cc9e56c93beb9c160d02 /src/mainboard/intel/shadowmountain/variants/baseboard | |
| parent | 50134eccbdf4878f03e64b8085832a86c5b928f0 (diff) | |
soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/variants/baseboard')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5b6a09710d..d5e5951c2a 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -118,21 +118,13 @@ chip soc/intel/alderlake register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" - register "DdiPortAHpd" = "1" - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "0" - register "DdiPort1Hpd" = "1" - register "DdiPort2Hpd" = "1" - register "DdiPort3Hpd" = "0" - register "DdiPort4Hpd" = "0" - - register "DdiPortADdc" = "0" - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "0" - register "DdiPort1Ddc" = "0" - register "DdiPort2Ddc" = "0" - register "DdiPort3Ddc" = "0" - register "DdiPort4Ddc" = "0" + # Enable Display Port Configuration + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" # Intel Common SoC Config #+-------------------+---------------------------+ |