diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-01-20 07:15:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-02-22 05:46:58 +0000 |
| commit | 738aaa24d38385b9ba8078d452dbaa4f36cdf4e6 (patch) | |
| tree | 99d3fd3ac9567dc4325a3a4b9e41259adf610b9f /src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | |
| parent | 43f6598b2781bd087a99626967a5186ecc2b9163 (diff) | |
mb/intel/shadowmountain: Add the romstage code
This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 1b3e37537b..088b595e93 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -17,6 +17,28 @@ chip soc/intel/alderlake register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 1 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR, + }" device domain 0 on device pci 00.0 on end # Host Bridge |