diff options
author | V Sowmya <v.sowmya@intel.com> | 2021-01-15 14:01:54 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-06 09:09:16 +0000 |
commit | 1b150cb000a189f7564486ec9411222718374111 (patch) | |
tree | dadcd64d385230fe4ead39c3714bc2ae19d98457 /src/mainboard/intel/shadowmountain/chromeos.c | |
parent | 72463720a2aa831c703e2536843f5f58ed32091d (diff) |
mb/intel/shadowmountain: Add bootblock and verstage code
This patch includes the bootblock and verstage changes for
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/chromeos.c')
-rw-r--r-- | src/mainboard/intel/shadowmountain/chromeos.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c new file mode 100644 index 0000000000..35a54a8aca --- /dev/null +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} |