From 1b150cb000a189f7564486ec9411222718374111 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 15 Jan 2021 14:01:54 +0530 Subject: mb/intel/shadowmountain: Add bootblock and verstage code This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra --- src/mainboard/intel/shadowmountain/chromeos.c | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 src/mainboard/intel/shadowmountain/chromeos.c (limited to 'src/mainboard/intel/shadowmountain/chromeos.c') diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c new file mode 100644 index 0000000000..35a54a8aca --- /dev/null +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} -- cgit v1.2.3