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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-19 12:31:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-21 07:16:01 +0000
commitf50ea988b09e7201e129848ab64e6e0e69bf56c4 (patch)
treee7cf17631d7c3cd41fa3c68a4c578d4ee7e36b8a /src/mainboard/intel/saddlebrook
parentdadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (diff)
soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
-rw-r--r--src/mainboard/intel/saddlebrook/gpio.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h
index 255f278db3..a574ac589d 100644
--- a/src/mainboard/intel/saddlebrook/gpio.h
+++ b/src/mainboard/intel/saddlebrook/gpio.h
@@ -75,7 +75,7 @@ static const struct pad_config gpio_table[] = {
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),
+/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1),
/* GSPI0_CS# */ /* GPP_B15 */
/* WLAN_PCIE_WAKE */
/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP),
@@ -84,11 +84,11 @@ static const struct pad_config gpio_table[] = {
/* CODEC_SPI_CLK */
/* CODEC_SPI_MISO */
/* CODEC_SPI_MOSI */
-/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1),
+/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF1),
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_NF(GPP_C2, DN_20K, DEEP, NF1),
/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
/* SML0ALERT# */ /* GPP_C5 */