mb/intel/saddlebrook: migrate to FSP 2.0

This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)

TODO:
- testing

Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923
Reviewed-by: Michael Niewöhner
Reviewed-by: Wim Vervoorn
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 13 insertions, 17 deletions

diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c
index 0ed6730b5c..8e280de638 100644
--- a/src/mainboard/intel/saddlebrook/romstage.c
+++ b/src/mainboard/intel/saddlebrook/romstage.c
@@ -24,10 +24,10 @@
 #include <spd_bin.h>
 
 
-void mainboard_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
 	struct spd_block blk = {
 		.addr_map = { 0x50, 0x52, },
 	};
@@ -36,26 +36,22 @@ void mainboard_memory_init_params(
 	dump_spd_info(&blk);
 	printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
 
-	memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
-	memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
-	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
-		memory_params->MemorySpdPtr00);
-	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
-		memory_params->MemorySpdPtr10);
+	mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
+	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00);
+	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10);
 
 	/*
 	* Configure the DQ/DQS settings if required. In general the settings
 	* should be set in the FSP flash image and should not need to be
 	* changed.
 	*/
-	mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0,
-				   &memory_params->DqByteMapCh1);
-	mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0,
-				    &memory_params->DqsMapCpu2DramCh1);
-	mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
-	mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
 
 	/* update spd length*/
-	memory_params->MemorySpdDataLen = blk.len;
-	memory_params->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->DqPinsInterleaved = TRUE;
 }