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| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-17 15:20:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-19 09:24:59 +0000 |
| commit | 93faff84cbc22a4cbf6edf0563409b2eeac16081 (patch) | |
| tree | abd6bd5ad372d696ad7214cc61d5d5ba03a8e1ff /src/mainboard/intel/saddlebrook/gpio.h | |
| parent | 80496f09670095acce4c7a002c28af5d6bc9198c (diff) | |
soc/lowrisc: Remove the remains of a LowRISC soc
Looks like we've got a race condition between commit ce8763fb with
Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d ("mb/lowrisc: Remove
the Nexys4DDR port") and commit 2e38dbe5 with Change-Id
I5524732f6eb3841e43afd176644119b03b5e5e27 ("riscv: update mtime
initialization"). Let's fix it.
Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29165
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook/gpio.h')
0 files changed, 0 insertions, 0 deletions