diff options
author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 04:14:03 +0200 |
---|---|---|
committer | Felix Singer <felixsinger@posteo.net> | 2024-06-24 14:23:13 +0000 |
commit | 842ee24340e1c643701ba04f11620dc7152a091b (patch) | |
tree | 06bc238d2f7c11b272e905400d32a9875658fe13 /src/mainboard/intel/saddlebrook/devicetree.cb | |
parent | 0c1daa59b902364d26f13290dff0e44bda839539 (diff) |
skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabled
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/saddlebrook/devicetree.cb')
-rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 6756d83485..d888de4a24 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -17,7 +17,6 @@ chip soc/intel/skylake # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |