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authorAnil Kumar <anil.kumar.k@intel.com>2023-10-24 14:22:51 -0700
committerMartin L Roth <gaumless@gmail.com>2023-11-01 15:34:11 +0000
commita8962492b224c84a48c041a414ccbc3b6e8e4869 (patch)
tree213dfe7be732ae285c5ed3d860d4f3ca432cd51a /src/mainboard/intel/mtlrvp
parentda48d9ebfe30d65348bd337bda1f502c91a71970 (diff)
mb/{google,intel}: Update FMD to support CBFS verification
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/intel/mtlrvp')
-rw-r--r--src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd2
-rw-r--r--src/mainboard/intel/mtlrvp/chromeos.fmd2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
index 6ca1cc68c0..d0856406a3 100644
--- a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
+++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
@@ -8,7 +8,6 @@ FLASH 32M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
- ME_RW_A(CBFS) 4400K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
@@ -18,7 +17,6 @@ FLASH 32M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
- ME_RW_B(CBFS) 4400K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd
index a5bc538873..c32a9f0675 100644
--- a/src/mainboard/intel/mtlrvp/chromeos.fmd
+++ b/src/mainboard/intel/mtlrvp/chromeos.fmd
@@ -8,7 +8,6 @@ FLASH 32M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
- ME_RW_A(CBFS) 4400K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
@@ -18,7 +17,6 @@ FLASH 32M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
- ME_RW_B(CBFS) 4400K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {