diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-02-04 10:35:50 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-02-07 05:42:02 +0000 |
| commit | 453805ceb948b1a8de545c4547b38bb45b5206ed (patch) | |
| tree | 84a156b577dcd0ab573d2d50258dde578cfded54 /src/mainboard/intel/mtlrvp/variants | |
| parent | 05ca3d18a8fe1f6ceb0d53ec5f146a944b52845d (diff) | |
mb/intel/mtlrvp: Enable PCIe port 8 for WLAN
This patch enables PCIe port for WLAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets
is enumerated as part of lspci in AP console.
ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE
Advanced Modem (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/mtlrvp/variants')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 1573cdffbb..53464f91b5 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -87,6 +87,14 @@ chip soc/intel/meteorlake .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, }" end # WWAN + device ref pcie_rp8 on + # Enable PCH PCIE RP 8 using CLK 5 + register "pcie_rp[PCIE_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + end # WLAN device ref pcie_rp10 on # Enable SSD Gen4 PCIE 10 using CLK 8 register "pcie_rp[PCIE_RP(10)]" = "{ |