diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-02-03 09:58:28 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-02-05 07:11:00 +0000 |
| commit | 7b8cbdd76bb28e2268fce39731f35d0207605caa (patch) | |
| tree | cd52e984618407dab76be5c07e4658aa840e6f1a /src/mainboard/intel/mtlrvp/variants/baseboard | |
| parent | 01c8c5936451d1f31dcb0a1c79f1f8e01dead83b (diff) | |
mb/intel/mtlrvp: Remove GPP_A12 for chrome platform
This patch removes the configuration of GPP_A12 for mtlrvp. Garfield
Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin
prevents system entering G3 (reboots) on issuing shutdown -h now. Hence
configuring GPP_A12 as PAD_NC.
BUG=b:224325352
BRANCH=None
TEST=On issuing 'shutdown -h now' system enters G3
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp/variants/baseboard')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c index 892a950309..2c48a0ece7 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c @@ -19,8 +19,8 @@ static const struct pad_config mtl_p_rvp_gpio_table[] = { /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ /* GPP_A11: PEG_SLOT_DGPU_SEL_N */ PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* GPP_A12: WIFI_WAKE_N */ - PAD_CFG_GPI_SCI(GPP_A12, NONE, DEEP, LEVEL, INVERT), + /* GPP_A12: NC */ + PAD_NC(GPP_A12, NONE), /* GPP_A13: M2_SSD2_RST_N */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPP_A14: M2_CPU_SSD4_RESET_N */ |