diff options
| author | Usha P <usha.p@intel.com> | 2023-03-02 20:48:51 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-04 06:21:14 +0000 |
| commit | fb1b192cf1c101dad40991081e406dddf52bd7fd (patch) | |
| tree | 9a8f72e7e6701d984f3da7427ded4548671c7285 /src/mainboard/intel/mtlrvp/chromeos.fmd | |
| parent | 5f7c9b68009932d841d00a35b48b5450f3623229 (diff) | |
mb/google/mtlrvp: Update MTLRVP Flash Layout
This patch updates the MTLRVP flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.
SI_BIOS:
SI_EC: Removed
RW_SECTION_A/B: Increased by ~1.9MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
Additionally, moved RW_LEGACY under extended BIOS region.
For chromeos-debug-fsp.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.2MB.
RW_LEGACY: Dropped
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
BUG=b:271407315
TEST=Able to enable CSE update on MTLRVP and have free space
to add one more PUNIT FW to support different SoC stepping.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp/chromeos.fmd')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos.fmd | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index 9fc7d7b2c8..22dbff587f 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -1,36 +1,34 @@ FLASH 32M { SI_ALL 9M { SI_DESC 16K - SI_EC 512K SI_ME } SI_BIOS 23M { - RW_SECTION_A 6M { - VBLOCK_A 64K + RW_SECTION_A 7092K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_LEGACY(CBFS) 2M - RW_MISC 1M { + RW_MISC 152K { UNIFIED_MRC_CACHE 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K } RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_NVRAM(PRESERVE) 8K } - RW_SECTION_B 6M { - VBLOCK_B 64K + RW_SECTION_B 7092K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } + RW_LEGACY(CBFS) 1M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 8M { |