diff options
| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
| commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
| tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/mainboard/intel/mtarvon/devicetree.cb | |
| parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) | |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel/mtarvon/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/mtarvon/devicetree.cb | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb deleted file mode 100644 index c1ff1d585a..0000000000 --- a/src/mainboard/intel/mtarvon/devicetree.cb +++ /dev/null @@ -1,45 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA479M - device lapic 0 on end - end - end -end |