diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-08-11 12:51:38 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-08-18 02:24:49 +0200 |
| commit | f7a7ec09d871c52bbf7cda016d2f814831de565e (patch) | |
| tree | e2bc4e276d84ea72a650002253215428d7fd46e5 /src/mainboard/intel/mohonpeak/romstage.c | |
| parent | 174a891121d5c474446a4fc1471387db454de6cf (diff) | |
mainboard/intel/mohonpeak: code cleanup
Code cleanup requested in commit 90957f88 -
"mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"
- Change com2 to COM2 in Kconfig text
- clean up includes of headers
- fix whitespace
Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/mohonpeak/romstage.c')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/romstage.c | 23 |
1 files changed, 7 insertions, 16 deletions
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index 73e54671c0..b1fb99502f 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -19,36 +19,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> -#include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include <northbridge/intel/fsp_rangeley/northbridge.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include <southbridge/intel/fsp_rangeley/gpio.h> #include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include "gpio.h" static void interrupt_routing_config(void) { - u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf; + u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf; - /* - * Initialize Interrupt Routings for each device in ilb_base_address. - * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. - * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. - * This should match devicetree and the ACPI IRQ routing/ - */ + /* + * Initialize Interrupt Routings for each device in ilb_base_address. + * IR01 map to PCIe device 0x01 ... IR31 to device 0x1F. + * PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23. + * This should match devicetree and the ACPI IRQ routing/ + */ write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */ write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */ write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */ |