diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-03 13:49:23 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-03 22:23:54 +0000 |
| commit | 959478a763c16688d43752adbae2c76e7764da45 (patch) | |
| tree | 2341da5033876b7358df78c9d570015794e9296f /src/mainboard/intel/mohonpeak/devicetree.cb | |
| parent | fb50124d22014742b6990a95df87a7a828e891b6 (diff) | |
Remove FSP Rangeley SOC and mohonpeak board support
mohonpeak is the reference board for Rangeley. I doubt anyone uses it
or cares about it. We jokingly refer to it as "Moron Peak". It's code
with no known users, so we shouldn't be hauling it around for the
eventuality that someone might use it in the future.
Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11790
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Diffstat (limited to 'src/mainboard/intel/mohonpeak/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/devicetree.cb | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb deleted file mode 100644 index 9874b98b68..0000000000 --- a/src/mainboard/intel/mohonpeak/devicetree.cb +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. -# -chip northbridge/intel/fsp_rangeley - - device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end - chip cpu/intel/fsp_model_406dx - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 1.0 on end # PCIe Port #1 - device pci 2.0 on end # PCIe Port #2 - device pci 3.0 on end # PCIe Port #3 - device pci 4.0 on end # PCIe Port #4 - chip southbridge/intel/fsp_rangeley # Rangeley SB - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x0f" - - register "fadt_pm_profile" = "PM_DESKTOP" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - device pci 0b.0 on end # IQIA - device pci 0e.0 on end # RAS - device pci 13.0 on end # SMBus 1 - device pci 14.0 on end # GbE 0 - device pci 14.1 on end # GbE 1 - device pci 14.2 on end # GbE 2 - device pci 14.3 on end # GbE 3 - device pci 16.0 on end # USB EHCI - device pci 17.0 on end # SATA 2.0 - device pci 18.0 on end # SATA 3.0 - device pci 1f.0 on end # LPC bridge - device pci 1f.3 on end # SMBus 0 - end - end -end |