diff options
| author | Martin Roth <gaumless@gmail.com> | 2014-05-21 14:23:12 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-07-30 19:01:20 +0200 |
| commit | 90957f885294527ff9342f56d2e07c5a23fb1ce2 (patch) | |
| tree | d968870ab97604d3582267fabf546af915a21455 /src/mainboard/intel/mohonpeak/devicetree.cb | |
| parent | 829c41da6cd9d8e9c9244c8c9ea2b181ea5ab930 (diff) | |
mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
Add the Mohon Peak CRB.
Updates to come.
Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6371
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/mohonpeak/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/devicetree.cb | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb new file mode 100644 index 0000000000..ee688b7c2a --- /dev/null +++ b/src/mainboard/intel/mohonpeak/devicetree.cb @@ -0,0 +1,68 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/intel/fsp_rangeley + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/fsp_model_406dx + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 1.0 on end # PCIe Port #1 + device pci 2.0 on end # PCIe Port #2 + device pci 3.0 on end # PCIe Port #3 + device pci 4.0 on end # PCIe Port #4 + chip southbridge/intel/fsp_rangeley # Rangeley SB + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x0f" + + register "fadt_pm_profile" = "PM_DESKTOP" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + device pci 0b.0 on end # IQIA + device pci 0e.0 on end # RAS + device pci 13.0 on end # SMBus 1 + device pci 14.0 on end # GbE 0 + device pci 14.1 on end # GbE 1 + device pci 14.2 on end # GbE 2 + device pci 14.3 on end # GbE 3 + device pci 16.0 on end # USB EHCI + device pci 17.0 on end # SATA 2.0 + device pci 18.0 on end # SATA 3.0 + device pci 1f.0 on end # LPC bridge + device pci 1f.3 on end # SMBus 0 + end + end +end |