mb/*/*: Drop Intel Rangeley mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 0 insertions, 26 deletions

diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
deleted file mode 100644
index aecc2b6905..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
-// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-
-	// Wake
-	Name(_PRW, Package(){0x1d, 0x05})
-}