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| author | Martin Roth <martin.roth@se-eng.com> | 2014-08-11 11:10:29 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-08-12 03:35:59 +0200 |
| commit | b40c345947d7891070f46f67e9ded65d74d58f7a (patch) | |
| tree | 78d25c5dbafcc1f4d2c73fda5c85b6807590574a /src/mainboard/intel/minnowmax | |
| parent | 9944b28cc478914233d9e555df6b9ab0cc46d097 (diff) | |
mainboard/intel/minnowmax: clean up includes & whitespace
Clean up as requested in commit e6df041b.
No functional changes.
Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6597
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax')
| -rw-r--r-- | src/mainboard/intel/minnowmax/romstage.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index 575e646862..460c668a9a 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -18,25 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#include <stddef.h> -#include <arch/cpu.h> -#include <lib.h> -#include <arch/io.h> -#include <arch/cbfs.h> -#include <arch/stages.h> -#include <console/console.h> -#include <cbmem.h> -#include <cpu/x86/mtrr.h> -#include <romstage_handoff.h> -#include <timestamp.h> -#include <baytrail/gpio.h> -#include <baytrail/iomap.h> -#include <baytrail/lpc.h> -#include <baytrail/pci_devs.h> #include <baytrail/romstage.h> -#include <baytrail/acpi.h> -#include <baytrail/baytrail.h> #include <drivers/intel/fsp/fsp_util.h> /** @@ -58,23 +40,19 @@ void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) } - /** * /brief mainboard call for setup that needs to be done after fsp init * */ - void late_mainboard_romstage_entry() { } - void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - /* Disable 2nd DIMM */ UpdData->PcdMrcInitSPDAddr2 = 0x00; |