diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:33:48 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:17 +0000 |
| commit | 298619f6d9adde49b4279c906b0d20a41f919a61 (patch) | |
| tree | 5f69fd9592a077a7b5e35a955bfc2e8b1b5370ea /src/mainboard/intel/littleplains/devicetree.cb | |
| parent | bc29bd0de65f1c2054117d42a9e3241ed4c3db80 (diff) | |
mb/*/*: Drop Intel Rangeley mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/mainboard/intel/littleplains/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/littleplains/devicetree.cb | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/src/mainboard/intel/littleplains/devicetree.cb b/src/mainboard/intel/littleplains/devicetree.cb deleted file mode 100644 index 0cb73f8a02..0000000000 --- a/src/mainboard/intel/littleplains/devicetree.cb +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/intel/fsp_rangeley - - device cpu_cluster 0 on - chip cpu/intel/fsp_model_406dx - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 1.0 on end # PCIe Port #1 - device pci 2.0 on end # PCIe Port #2 - device pci 3.0 on end # PCIe Port #3 - device pci 4.0 on end # PCIe Port #4 - chip southbridge/intel/fsp_rangeley # Rangeley SB - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x0f" - - register "fadt_pm_profile" = "PM_DESKTOP" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" - - device pci 0b.0 on end # IQIA - device pci 0e.0 on end # RAS - device pci 13.0 on end # SMBus 1 - device pci 14.0 on end # GbE 0 - device pci 14.1 on end # GbE 1 - device pci 14.2 on end # GbE 2 - device pci 14.3 on end # GbE 3 - device pci 16.0 on end # USB EHCI - device pci 17.0 on end # SATA 2.0 - device pci 18.0 on end # SATA 3.0 - device pci 1f.0 on end # LPC bridge - device pci 1f.3 on end # SMBus 0 - end - end -end |