diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:33:48 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:17 +0000 |
| commit | 298619f6d9adde49b4279c906b0d20a41f919a61 (patch) | |
| tree | 5f69fd9592a077a7b5e35a955bfc2e8b1b5370ea /src/mainboard/intel/littleplains/Kconfig | |
| parent | bc29bd0de65f1c2054117d42a9e3241ed4c3db80 (diff) | |
mb/*/*: Drop Intel Rangeley mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/mainboard/intel/littleplains/Kconfig')
| -rw-r--r-- | src/mainboard/intel/littleplains/Kconfig | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig deleted file mode 100644 index b5a57b798b..0000000000 --- a/src/mainboard/intel/littleplains/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_LITTLEPLAINS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select NORTHBRIDGE_INTEL_FSP_RANGELEY - select SOUTHBRIDGE_INTEL_FSP_RANGELEY - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - -config MAINBOARD_DIR - string - default intel/littleplains - -config MAINBOARD_PART_NUMBER - string - default "Little Plains" - -config MAX_CPUS - int - default 16 - -config CBFS_SIZE - hex - default 0x400000 - -config ENABLE_FSP_FAST_BOOT - bool - depends on HAVE_FSP_BIN - default y - -config FSP_PACKAGE_DEFAULT - bool "Configure defaults for the Intel FSP package" - default n - -config UART_FOR_CONSOLE - int - default 1 - help - The Little Plains board uses COM2 (2f8) for the serial console. - -config PAYLOAD_CONFIGFILE - string - depends on PAYLOAD_SEABIOS - default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" - help - The Avoton/Rangeley chip does not allow devices to write into the 0xe000 - segment. This means that USB/SATA devices will not work in SeaBIOS unless - we put the SeaBIOS buffer area down in the 0x9000 segment. - -endif # BOARD_INTEL_LITTLEPLAINS |