diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-21 03:46:58 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-21 18:50:01 +0000 |
| commit | 3840bcc19e28401e5fd4e3b4c0f0d1438fbbdeed (patch) | |
| tree | eb5059578c181875c011338a1289261dbfcccf62 /src/mainboard/intel/leafhill/brd_gpio_early.h | |
| parent | 9c27dc8d5683f8a09f10e249cbd577058f1da15c (diff) | |
mb/intel/leafhill: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ibc727302109456eb1d86652c947ce85b3a64c5b2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49436
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/leafhill/brd_gpio_early.h')
| -rw-r--r-- | src/mainboard/intel/leafhill/brd_gpio_early.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/intel/leafhill/brd_gpio_early.h b/src/mainboard/intel/leafhill/brd_gpio_early.h index e44bc706fa..8b40f53721 100644 --- a/src/mainboard/intel/leafhill/brd_gpio_early.h +++ b/src/mainboard/intel/leafhill/brd_gpio_early.h @@ -12,5 +12,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1), + + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ }; |