diff options
| author | Alexander Goncharov <chat@joursoir.net> | 2023-02-04 15:20:37 +0400 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-07 04:37:31 +0000 |
| commit | 893c3ae892961facc9be8bd300160222e694ab34 (patch) | |
| tree | ec628a8f9371fe96b783c7bf11dee59d065c0df5 /src/mainboard/intel/kblrvp | |
| parent | db4b71ff10b48624a1a0b76e3255bd206ef921d5 (diff) | |
tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp')
3 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index df35e8a9f9..d512814023 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -10,37 +10,37 @@ chip soc/intel/skylake register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses uses CLK SRC 2 + # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses uses CLK SRC 3 + # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses uses CLK SRC 4 + # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses uses CLK SRC 5 + # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses uses CLK SRC 7 + # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" # USB related diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b1d291722b..2c93a38921 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -41,21 +41,21 @@ chip soc/intel/skylake register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses uses CLK SRC 2 + # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses uses CLK SRC 3 + # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" # PCIE Port 7 Disabled @@ -64,14 +64,14 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses uses CLK SRC 5 + # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses uses CLK SRC 4 + # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" # USB 2.0 Enable all ports diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 5c5382fbaa..23cbf96f40 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -101,15 +101,15 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkReqNumber[8]" = "1" - # RP 3 uses uses CLK SRC 5# + # RP 3 uses CLK SRC 5# register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses uses CLK SRC 2# + # RP 4 uses CLK SRC 2# register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses uses CLK SRC 3# + # RP 5 uses CLK SRC 3# register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses uses CLK SRC 4# + # RP 6 uses CLK SRC 4# register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses uses CLK SRC 1# + # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports |