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authorAngel Pons <th3fanbus@gmail.com>2021-08-29 10:10:29 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-06 19:09:51 +0000
commit7b615f8eebb491e1d81db149089075612bbde14e (patch)
tree0c571e8d0932dc5319134cd3aa0122458030f78c /src/mainboard/intel/kblrvp/variants/rvp8
parentc7e2e485b3634e3f62ee9f6ce57198cc55a05eb2 (diff)
mb/intel/kblrvp: Do not use Legacy mode for UART #2
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as coreboot console. However, the LPSS console driver requires the LPSS UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs). KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most likely results in the UART console not working after FSP-S has run. This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like the other KBLRVP variants do. Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp8')
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 00690fa8c7..4bb00dd6ce 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -147,7 +147,7 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
# PL2 override 25W