diff options
author | Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2019-01-04 01:10:25 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 10:01:25 +0000 |
commit | 7e48b47185d72e9a0c6bee5bab352d3c819dafe4 (patch) | |
tree | 80563a9d6a8149f85f6796cf2ab6948ecf271a92 /src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | |
parent | e81880dd0d188867b4fb4d1d89584d5e2026c041 (diff) |
mb/intel/kblrvp: Enable overridetree support for variants
This patch add devicetree.cb in baseboard and overridetree.cb
for RVP3, RVP7 and RVP8 variants.
BUG= None
TEST= build with BUILD_TIMELESS=1, static.c remains same on before &
after enabling overridetree.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ib7d492e2a92aed10ad0426d57640d0ed56733847
Reviewed-on: https://review.coreboot.org/c/30623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb')
-rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 179 |
1 files changed, 179 insertions, 0 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb new file mode 100644 index 0000000000..9753c64e26 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -0,0 +1,179 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + + # FSP Configuration + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "PmTimerDisabled" = "0" + register "SerialIrqConfigSirqMode" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + # Enable Root port. + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[16]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + + # SRCCLKREQ# + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkReqNumber[4]" = "1" + register "PcieRpClkReqNumber[8]" = "6" + register "PcieRpClkReqNumber[16]" = "7" + + register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel + register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel + register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1 + register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel + register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT + register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1 + register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel + register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Use default SD card detect GPIO configuration + #register "sdcard_cd_gpio_default" = "GPP_D10" + + device domain 0 on + device pci 17.0 on end # SATA + device pci 19.1 on end # I2C #5 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1f.0 on + #chip drivers/pc80/tpm + # device pnp 0c31.0 on end + #end + end # LPC Interface + device pci 1f.6 on end # GbE + end +end |