diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-07-08 04:29:39 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-12 20:08:01 +0000 |
| commit | 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch) | |
| tree | 9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/intel/kblrvp/variants/rvp7 | |
| parent | 702902d71fae63fd35362c82f2a369b42af1a77f (diff) | |
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp7')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb | 67 |
1 files changed, 30 insertions, 37 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 99963bf829..c4f8d46dbb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -72,39 +72,6 @@ chip soc/intel/skylake .voltage_limit = 0 }" - # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - - # RP 3 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[2]" = "5" - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkReqNumber[5]" = "4" - register "PcieRpClkReqNumber[8]" = "1" - - # RP 3 uses CLK SRC 5# - register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses CLK SRC 2# - register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses CLK SRC 3# - register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses CLK SRC 4# - register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses CLK SRC 1# - register "PcieRpClkSrcNumber[8]" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -156,10 +123,36 @@ chip soc/intel/skylake [2] = 1, }" end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkSrcNumber[2]" = "5" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkSrcNumber[3]" = "2" + end + device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + end + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + end device ref lpc_espi on # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" |