diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395bd1..81557eb8ff 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -74,26 +74,6 @@ chip soc/intel/skylake # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ - [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ - [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ - [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ - }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -113,6 +93,28 @@ chip soc/intel/skylake }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + }" + end device ref imgu on end device ref cio on end device ref pcie_rp1 on end # x4 SLOT1 |