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authorFurquan Shaikh <furquan@chromium.org>2017-10-06 17:05:50 -0700
committerFurquan Shaikh <furquan@google.com>2017-10-09 20:20:40 +0000
commit219ebb969bb52eb88d49d6ce31dbfc0d7cabfc49 (patch)
tree5597f190251338d86df7ee8706faa765d9ee4d5c /src/mainboard/intel/kblrvp/variants/rvp3/include
parente9d8959c4f11399c7ec1609ecff204c8f3c9b3ea (diff)
skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp3/include')
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
index c6f41234ef..64d0259404 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
@@ -48,7 +48,7 @@ static const struct pad_config gpio_table[] = {
/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
+/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
@@ -67,7 +67,7 @@ static const struct pad_config gpio_table[] = {
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0),
/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1),
-/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+/* GP_VRALERTB */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5),
@@ -122,10 +122,10 @@ static const struct pad_config gpio_table[] = {
/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP),
-/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
-/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
-/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+/* HOME_BTN */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, DEEP),
+/* SCREEN_LOCK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),
+/* VOL_UP_PCH */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),
+/* VOL_DOWN_PCH */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),
/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
@@ -139,7 +139,7 @@ static const struct pad_config gpio_table[] = {
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
-/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+/* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),
/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP),
/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),